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背栅OFET基板,Back-gated OFET Substrate;n-doped silicon wafer with 230 nm SiO2 gate-insulator, chips (diced)

背栅OFET基板(有机场效应晶体管)可用于制造化学传感器,用于pH传感和免疫测定检测,还可用于制造生物传感器。
制造商品牌: 西格玛 Sigma-Aldrich
货号(SKU): FIPMS176
增值税发票 √ 免费送货 √ 订货电话:010-68689484
¥12,140.05

说明

背栅 OFET 基板(有机场效应晶体管)可用于制造化学传感器,用于 pH 传感和免疫测定检测。它还可用于制造生物传感器,方法是在 FET 的薄片上涂上用于检测 SARS-CoV-2 的特异性抗体。基于 FET 的生物传感器可潜在地用于临床诊断、护理点测试和现场检测。
对于有机半导体领域的材料科学家来说,拥有用于材料分析的标准化设备架构至关重要。

这些背栅有机场效应晶体管 (OFET) 基板是在洁净室内制造的,源极和漏极电极可以在有机半导体材料沉积之前或之后沉积,从而为源/漏极材料的选择和满足不同的首选设备架构。

当有机半导体层沉积在这样的基板上时,体硅充当栅电极并控制顶部沉积后源电极和漏电极之间的沟道电流。 CMOS 质量的适当掺杂的 Si-SiO2 界面保证了可再现的栅极接触。

一般描述

Substrate: 150 mm wafer according to semiconductor standard (used for bottom-gate)
Layer structure:
  • Gate: n-doped silicon (doping at wafer surface: n~3x1017/ cm3)
  • Gate oxide: 230 nm ± 10 nm SiO2 (thermal oxidation)
  • Drain/source:none
  • Protection: resist AR PC 5000/3.1 (soluble in AZ-Thinner or acetone)
  • Layout: bare oxide but diced
  • Chip size: 15 x 15 mm2
  • No. of chips: 60 per wafer

应用

Back-gated OFET Substrate (organic field-effect transistor) can be used in the fabrication of chemical sensors for potential usage in pH sensing and detection of immunoassays. It can also be used in the fabrication of biosensors by coating the sheets of the FET with a specific antibody for the detection of SARS-CoV-2. FET based biosensors can be potentially used in clinical diagnosis, point of care testing, and on-site detection.
For material scientists in the field of organic semiconductors, it is critically important to have standardized device architecture for material analysis.

These back-gated organic filed-effect transistor (OFET) substrates were fabricated inside the cleanroom, and source and drain electrodes can be deposited either prior or after the deposition of an organic semiconductor material, giving versatility for the choice of source/drain materials and satisfy different preferred device architectures.

When an organic semiconductor layer is deposited on such a substrate, the bulk Si acts as gate electrode and controls the channel current between the post-deposited source and drain electrodes on the top. A suitably doped Si-SiO2 interface in CMOS quality guarantees a reproducible gate contact.
 

包装

diced wafer on foil with air tight packaging
 

制备说明

Recommendation for resist removal:
To guarantee a complete cleaning of the wafer / chip surface from resist residuals, please rinse by acetone and then dry the material immediately by nitrogen (compressed air).

Recommendation for material characterization:
If gate currents appear during the characterization of the field effect transistors, considerable variations could occur at the extraction of the carrier mobility. Therefore it is necessary to check the leakage currents over the reverse side (over the chip edges) of the OFET-substrates.
 

储存及稳定性

Store the wafers at a cool and dark place and protect them against sun.Resist layer was applied to prevent damage from scratches. Expiration date is the recommended period for resist removal only. After resist removal, the substrate remains functional and does not expire.
 

法律信息

Product of Fraunhofer IPMS
 
 

属性

形式

chips (diced)
chips (each 15 x 15 mm2)

包装

pack of 1 (wafer of 60 diced chips)

 

安全信息

监管信息

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商品规格
属性名称属性值
储存温度 Storage temp.常温阴凉避光
全球实时库存 Availability √美国St. Louis ≥ 55 | 欧洲Eur. ≥ 16 | 東京Tokyo ≥ 8 | 香港与北京 ≥ 10